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Documentation Status

🚧 The UDB documentation site is under active construction. This page tracks the completion status of all planned documentation sections, so you can see at a glance what exists and what's coming.

Status Legend

  • Complete — Documentation is written, reviewed, and ready to use
  • 🚧 In Progress — Partially complete; some sections may be missing or outdated
  • 📋 Planned — Documentation is planned but not yet written

Introduction

SectionStatusNotes
What is UDB?✅ CompleteCore overview complete
Current State📋 PlannedMaturity and use case coverage

Getting Started

SectionStatusNotes
For Users📋 PlannedCLI, Ruby gem, Python bindings
For Specification Writers📋 PlannedAdding extensions, instructions, CSRs
For Developers📋 PlannedContributing code, writing generators
FAQ / How-Do-I📋 PlannedCommon questions and solutions

Concepts

SectionStatusNotes
Configurations🚧 In ProgressOverview exists, details pending
Data Pipeline📋 PlannedOverlay merge, resolution, inheritance
Conditions System📋 PlannedHow conditions work in the database

The Database (spec/)

SectionStatusNotes
Overview📋 PlannedDatabase structure and organization
Table Reference📋 PlannedDocumentation for each table
Custom Overlays📋 PlannedHow to customize the database
Schema Reference🚧 In ProgressAuto-generated from JSON Schema

IDL Language

SectionStatusNotes
Overview✅ CompleteCore concepts and use cases
Data Types✅ CompleteBits, Boolean, structs, enums
Literals✅ CompleteInteger, array, string literals
Operators✅ CompleteFull precedence table
Variables & Constants✅ CompleteDeclaration and usage
Type Conversions✅ CompleteCasting and implicit conversions
Builtins✅ CompleteBuilt-in functions reference
Control Flow✅ Completeif/else, loops, switch
Functions✅ CompleteDeclaration, calls, generated functions
Scope Rules✅ CompleteVariable and function scoping
In Instructions✅ CompleteHow IDL appears in instruction definitions
In CSRs✅ CompleteCSR-specific IDL usage
For Spec Writers✅ CompleteGuide for writing IDL specs
For C Users✅ CompleteIDL from a C perspective
For Verilog Users✅ CompleteIDL from a hardware perspective
Common Misunderstandings✅ CompleteFAQ and gotchas
Quick Reference✅ CompleteCheat sheet
Standard Library✅ CompleteStandard library functions
idlc Compiler🚧 In ProgressCompiler tool documentation

Tools

SectionStatusNotes
Overview📋 PlannedTool ecosystem overview
udb gem📋 PlannedMain database interface
udb-gen gem📋 PlannedArtifact generation
idlc gem📋 PlannedIDL compiler
udb_helpers gem📋 PlannedTemplate helpers
idl_highlighter gem📋 PlannedSyntax highlighting
bin/generate📋 PlannedGenerator wrapper script
bin/regress📋 PlannedRegression test runner
bin/chore📋 PlannedRepository maintenance

Generators

SectionStatusNotes
Overview📋 PlannedWhat generators produce
PRM PDF📋 PlannedProgrammer's Reference Manual
HTML Config Docs📋 PlannedConfiguration documentation
C++ ISS📋 PlannedInstruction Set Simulator
C Header📋 PlannedEncoding headers
Go📋 PlannedGo definitions
SystemVerilog📋 PlannedDecode packages
Profile Docs📋 PlannedRISC-V profile documentation
Instructions Appendix📋 PlannedAsciiDoc instruction appendix

Contributing

SectionStatusNotes
Code Contributions📋 PlannedHow to contribute code
Data Contributions📋 PlannedAdding spec data
Commit Conventions📋 PlannedCommit message format
Code Review📋 PlannedReview process
Docs Site Architecture📋 PlannedHow this site is built

Timeline

This documentation is being written incrementally as the site is built. The IDL language documentation is mostly complete (converted from existing AsciiDoc sources), while other sections are being written from scratch.

Priority order:

  1. Introduction and Getting Started (enabling new users)
  2. Concepts (understanding the architecture)
  3. Tools and Generators (practical usage)
  4. Database reference (for advanced users)
  5. Contributing guides (for contributors)

Check back regularly for updates, or watch the repository to be notified of new documentation.